1. Field of the Invention
The present invention relates to a memory control apparatus for a digital signal processor (DSP) having a pipeline structure, and in particular to an improved memory control apparatus for a digital signal processor having a pipeline structure which is capable of implementing a fast storing and computing operation by providing a cache memory for temporarily storing a data inputted through a decoder.
2. Description of the Background Art
FIG. 1 illustrates the construction of a conventional memory control apparatus for a digital signal processor (DSP) having a pipeline structure. As shown therein, the conventional memory control apparatus for a DSP having a pipeline structure includes a ROM (Read Only Memory) 40 for storing an execution program therein, a data storing block 30 provided with a plurality of RAMs (Random Access Memories) for storing a computation data therein, a decoder 10 for decoding an instruction INST and a data DATA and outputting a control code CTL, an address ADDR and a data DATA based on the decoding operation, and a memory management unit 20 for receiving the control code CTL, address ADDR and data from the decoder 10 and controlling an input/output operation of a data of the ROM 40.
Differently from the common processor, since the digital signal processor performs a computation based on an accumulator and a product register, a result of the computation is frequently stored in the memory. Therefore, the DSP processor has a three-step pipeline structure as shown in FIG. 2 or a four-step pipeline structure as shown in FIG. 3 for enabling a high speed data processing operation.
The processor having a three-step pipeline structure is performed by the following steps: an instruction fetch (IF) step in which an instruction to be executed is read, a decoding (D) step in which the read instruction is decoded, and an execution (E) step. Since the data which is used during the computation operation should be generated between the decoding step and the execution step, it is impossible to enable a high speed operation which is required in an application algorithm, and in addition, since more than one clock signal is internally used, it is impossible to maintain a uniformity of a design.
Therefore, in order to overcome the above-described problems, a four-step pipeline structure including a step for reading data is mainly used.
The DSP processor adapting the four-step pipeline structure performs the following steps: an instruction fetch (IF) step, a decoding (D) step, an operand fetch (OF) step in which a data used for a computation is read, and an execution step (E).
The operation of the conventional apparatus in which the fourth step is executed will be explained.
The decoder 10 decodes an instruction inputted and transfers a control code CTL, an address ADDR and a data DATA to a memory management unit 20, respectively, based on the decoding operation. The memory management unit 20 judges the control code CTL and activates a corresponding memory among an N-number of RAMs or ROM40 of the data storing block 30, or ROM 40 which corresponding memory is designated by the address ADDR. Therefore, a new data is stored into a corresponding memory, or the stored data is externally outputted through a data bus, so that an operation can be externally performed.
When an addition instruction is read in the instruction fetch (IF) step of the first pipeline line I of FIG. 3, and an addition operation is performed in the execution step (E), the operational result value is stabilized in the execution step (E). If a storing instruction is read in an instruction fetch (IF) step of a second pipe (II), the memory management unit 20 activates a memory designated by an address (ADDR) in a number N of RAMs or ROMs of the data storing block 30 during the operand fetch (OF) step, when a computation result value is stabilized. The computation result value is stored in the activated memory. The time when the operational result is stored into an accumulator or an accumulating register corresponds to the operand fetch (OF) step which is indicated by * as shown in FIG. 3. In addition, the accumulator and accumulating register (not shown) are connected with the data bus BUS.
Since the time when the value from the accumulator or accumulating register is stabilized is later than the operand fetch (OF) step of the next instruction, namely, since the time when the data is stored is earlier than the time when the data to be stored is stabilized, one cycle is further needed so that the instruction is executed for storing the data. Therefore, in the operand fetch (OF) step (*), the data are not stored. Namely, the data are stored in the operand fetch (OF) step (**) of the third pipeline III. In addition, the addition operation after the storing step is performed in the operand fetch (OF) step (***) of the fourth pipeline IV.
Therefore, one cycle is further needed for a data computation. In addition, for the data storing operation, one cycle is further needed, so that two cycles are totally needed for the data storing operation, and thus the system operation is delayed due to the extended data storing time.
In the DSP in which a computation is performed based on the accumulator, since all computations are performed based on the accumulator or accumulating register, and there are many steps for storing the data, the delay time which occurs in the data storing step becomes an important factor by which the processing performance of the DSP is decreased.
Accordingly, it is an object of the present invention to provide a memory control apparatus for a digital signal processor (DSP) having a pipeline structure which overcomes the aforementioned problems encountered in the background art.
It is another object of the present invention to provide memory control apparatus for a digital signal processor having a pipeline structure which is capable of implementing a fast storing and computing operation by providing a cache memory for temporarily storing a data inputted through a decoder.
To achieve the above objects, there is provided a memory control apparatus for a digital signal processor (DSP) having a pipeline structure, including: a ROM (Read Only Memory) for storing an execution program therein; a data storing block composed of a plurality of RAMs (Random Access Memories) for storing data therein; a decoder for decoding an instruction and associated data and outputting a control code, address and the associated data; a memory management unit; a judging unit for comparing the control code and the address outputted from the decoder with a previously stored control code and address, respectively, outputting an enable signal if the compared addresses are the same based on the comparison, and outputting the previously stored control code and address to the memory management unit if the compared addresses are not the same; and a cache memory for storing the associated data from the decoder, outputting the stored data to the outside through a data bus in accordance with a logic state of the enable signal and outputting the stored data to the memory management unit; wherein the memory management unit receives the previously stored control code and address from the judging unit and the stored data from the cache memory and controls data transfer to and from the data storing block and ROM.
Additional advantages, objects and features of the invention will become more apparent from the description which follows.